1. Technical Field
The present disclosure generally relates to integrated circuit die packaging, and in particular, to packaging multiple semiconductor dice in a stacked configuration.
2. Description of the Related Art
A trend in microelectronics packaging of integrated circuit (IC) chips is reduction of the electronic package dimensions—both the package footprint and the package thickness—while continuing to provide greater functionality. To address the need for size reduction, it is now customary to attach layered stacks of multiple IC chips, also called dies or dice, to printed circuit boards (PCBs). The chips may be stacked, for example, in a pyramidal configuration.
The stacked chips are secured physically to one another, and are surface-mounted to the PCB by an adhesive die attach film (DAF). Electrical connections between the PCB and a chip at the base of the stack are made by forming a two-dimensional array of solder balls, or ball grid array (BGA), on the underside of the base chip. The solder ball array is then placed in contact with metal interconnects patterned on a top metal layer of the PCB. Alternatively, an array of contact pads, such as a land grid array (LGA) or an ultra-fine land grid array (uFLGA) can be used instead of a BGA. Direct electrical connections between dice in a stacked configuration can be made using wire bonds. Additional wire bonds can be used to couple the layered stacks to one another via interconnects formed in the top metal layer.
PCBs bearing stacked chips can then be installed in, for example, mobile electronic devices such as smart phones, tablet computers, global positioning system (GPS) mapping devices, digital cameras, and the like. Each generation of mobile devices demands smaller and thinner electronic packages, while providing more functions to consumers. Enhanced functionality requires more complex integrated circuits, and more dice stacked into the electronic package. Semiconductor packages that accommodate stacked die configurations are described in further detail in U.S. Pat. Nos. 7,616,451 and 8,411,457, and in U.S. Patent Application Publication No. US2013/0170166 to Ziglioli et al., and assigned to the same assignee as the present patent application.